PPU rewrite
This commit is contained in:
FyloZ
parent
dcb01b4c6a
commit
eb0e0a42c0
GPG Key ID:
835378AE9AF4AE97
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@ -98,7 +98,7 @@ void mem_set_byte(address addr, byte data) {
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byte ppu_reg = relative_addr % 8;
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ppu_write_reg(ppu_reg, data);
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} else if (addr == PPU_REGISTER_OAM_DMA_ADDR) {
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ppu_write_reg_oam_addr(data);
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ppu_write_oamaddr(data);
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// Writing to this address triggers an upload to the PPU memory
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cpu_trigger_oam_dma();
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@ -30,7 +30,7 @@ bool gui_init() {
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return false;
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}
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gui.debug_enabled = true;
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gui.debug_enabled = false;
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main_window_init(&gui.main_window, gui.font);
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@ -35,13 +35,13 @@ void main_window_render_delay(SDL_Renderer *renderer) {
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char_map_render(renderer, buffer);
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}
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void main_window_render(NesMainWindow *window, PpuPixel *pixels) {
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void main_window_render(NesMainWindow *window, PPUPixel *pixels) {
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SDL_RenderClear(window->sdl_context.renderer);
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unsigned int frame_buffer[240 * 256];
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for (int i = 0; i < 240 * 256; i++) {
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PpuPixel pixel = pixels[i];
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PPUPixel pixel = pixels[i];
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unsigned int *data = &frame_buffer[i];
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*data = 0xff000000;
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@ -9,8 +9,8 @@
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#include "../include/ppu.h"
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#include "window.h"
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#define MAIN_WINDOW_WIDTH 240
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#define MAIN_WINDOW_HEIGHT 256
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#define MAIN_WINDOW_WIDTH 256
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#define MAIN_WINDOW_HEIGHT 240
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#define MAIN_WINDOW_SCALE 2
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typedef struct nes_main_window {
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@ -22,7 +22,7 @@ typedef struct nes_main_window {
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void main_window_init(NesMainWindow *window, TTF_Font *font);
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void main_window_uninit(NesMainWindow *window);
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void main_window_render(NesMainWindow *window, PpuPixel* pixels);
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void main_window_render(NesMainWindow *window, PPUPixel* pixels);
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void main_window_present(NesMainWindow *window);
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#endif //NES_EMULATOR_MAIN_WINDOW_H
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@ -73,11 +73,17 @@ typedef struct ppu_pixel {
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byte r;
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byte g;
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byte b;
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} PpuPixel;
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} PPUPixel;
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typedef struct ppu_tile_queue {
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PPUTileFetch first_fetch;
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PPUTileFetch second_fetch;
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PPUTileFetch displayed_fetch;
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} PPUTileQueue;
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typedef struct ppu {
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PPUMemory memory;
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PpuPixel pixels[256 * 240];
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PPUPixel pixels[256 * 240];
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byte registers[8];
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byte oam_dma_register;
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@ -88,10 +94,19 @@ typedef struct ppu {
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byte x;
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bool w;
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address ppu_address;
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byte x_scroll;
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byte fine_x_scroll;
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byte y_scroll;
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byte ppu_addr_increment;
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PPUTileFetch tile_fetch;
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PPUTileFetch next_tile_fetch;
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address ppu_address;
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address temp_ppu_addr;
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address bg_pattern_table_addr;
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PPUTileFetch fetch;
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PPUTileQueue tile_queue;
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// PPUTileFetch tile_fetch;
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// PPUTileFetch fetch;
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unsigned long frame;
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unsigned int scanline;
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unsigned int cycle;
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@ -138,7 +153,7 @@ byte ppu_read_reg(byte reg);
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void ppu_write_reg(byte reg, byte data);
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void ppu_write_reg_oam_addr(byte data);
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void ppu_write_oamaddr(byte data);
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void ppu_write(address addr, byte data);
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2
main.c
2
main.c
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@ -23,7 +23,7 @@
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#include "gui.h"
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int main() {
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char *rom_path = "../test_roms/dk_japan.nes";
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char *rom_path = "../test_roms/dk_jp.nes";
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log_set_level(LOG_INFO);
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if (!gui_init()) {
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391
ppu/ppu.c
391
ppu/ppu.c
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@ -19,7 +19,6 @@
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#include "../include/ppu.h"
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#include "../cpu/cpu.h"
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#include "../include/rom.h"
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#include "../gui/gui.h"
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#include "pattern_table.h"
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#define PPU_VISIBLE_FRAME_END 240
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@ -76,82 +75,153 @@ static inline unsigned int ppu_pixel_get_index(unsigned int scanline, unsigned i
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return scanline * PPU_VISIBLE_FRAME_END + cycle;
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}
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static inline byte ppu_pixel_get_mask(unsigned int cycle) {
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byte tile_fine_x = (cycle - 1) % 8;
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static inline byte ppu_pixel_get_mask(unsigned int tile_fine_x) {
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return 1 << (PATTERN_TILE_SIZE - tile_fine_x - 1);
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}
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static inline void ppu_pixel_set_color(PpuPixel *pixel, byte pt_low, byte pt_high, byte bitmask) {
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static inline void ppu_pixel_set_color(PPUPixel *pixel, byte pt_low, byte pt_high) {
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for (int i = 0; i < 8; i++) {
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PPUPixel *spixel = pixel + i;
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byte bitmask = ppu_pixel_get_mask(i);
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byte p1_byte = pt_low & bitmask;
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byte p2_byte = pt_high & bitmask;
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if (p1_byte && p2_byte) {
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pixel->r = 255;
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pixel->g = 255;
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pixel->b = 255;
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spixel->r = 255;
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spixel->g = 255;
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spixel->b = 255;
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} else if (p2_byte) {
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pixel->r = 255;
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pixel->g = 0;
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pixel->b = 0;
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spixel->r = 255;
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spixel->g = 0;
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spixel->b = 0;
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} else if (p1_byte) {
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pixel->r = 0;
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pixel->g = 255;
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pixel->b = 255;
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spixel->r = 0;
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spixel->g = 255;
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spixel->b = 255;
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} else {
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pixel->r = 0;
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pixel->g = 0;
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pixel->b = 0;
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spixel->r = 0;
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spixel->g = 0;
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spixel->b = 0;
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}
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}
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}
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void ppu_draw_tile() {
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PPUTileFetch tile_fetch = ppu_state.tile_fetch;
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PPUTileFetch fetch = ppu_state.tile_queue.displayed_fetch;
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unsigned int pixel_index = ppu_pixel_get_index(ppu_state.scanline, ppu_state.cycle);
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PpuPixel *pixel = &ppu_state.pixels[pixel_index];
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byte pixel_mask = ppu_pixel_get_mask(ppu_state.cycle);
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ppu_pixel_set_color(pixel, tile_fetch.pattern_table_tile_low, tile_fetch.pattern_table_tile_high, pixel_mask);
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unsigned int pixel_index = ppu_state.scanline * PPU_VISIBLE_FRAME_END + ppu_state.cycle;
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PPUPixel *pixel = &ppu_state.pixels[pixel_index];
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ppu_pixel_set_color(pixel, fetch.pattern_table_tile_low, fetch.pattern_table_tile_high);
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}
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byte ppu_get_pattern(byte tile_index, byte high) {
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byte tile_row_index = (ppu_state.scanline + ppu_state.y_scroll) % 8;
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address pattern_addr = ppu_state.bg_pattern_table_addr | tile_index << 4 | high << 3 | tile_row_index;
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return ppu_read(pattern_addr);
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}
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void ppu_fetch_tile() {
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byte fetch_cycle = (ppu_state.cycle - 1) % 8;
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if (fetch_cycle == 1) {
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address nametable_addr = (ppu_state.ppu_address & 0xfff) | 0x2000;
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ppu_state.fetch.nametable = ppu_read(nametable_addr);
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} else if (fetch_cycle == 3) {
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// PPU address:
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// yyy NN YYYYY XXXXX
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// ||| || ||||| +++++-- coarse X scroll
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// ||| || +++++-------- coarse Y scroll
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// ||| ++-------------- nametable select
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// +++----------------- fine Y scroll
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//
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// The attribute table is at the end of the nametable and contains 64 bytes
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// It controls the palette assignation of a 4x4 tiles area
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byte tile_col = ppu_state.ppu_address & 0x1f;
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byte tile_attr_col = (tile_col >> 2) & 0x7;
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byte tile_row = (ppu_state.ppu_address & 0x3e0) >> 5;
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byte tile_attr_row = (tile_row >> 2) & 0x7;
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// 0x23c0 is the base address of the first attribute table
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address attr_addr = 0x23c0 | (ppu_state.ppu_address & 0x0c00) | (tile_attr_row << 3) | tile_attr_col;
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ppu_state.fetch.attribute_table = ppu_read(attr_addr);
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} else if (fetch_cycle == 5) {
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ppu_state.fetch.pattern_table_tile_low = ppu_get_pattern(ppu_state.fetch.nametable, 0);
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} else if (fetch_cycle == 7) {
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ppu_state.fetch.pattern_table_tile_high = ppu_get_pattern(ppu_state.fetch.nametable, 1);
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ppu_state.tile_queue.displayed_fetch = ppu_state.fetch;
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ppu_draw_tile();
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if ((ppu_state.ppu_address & 0x1f) == 0x1f) {
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ppu_state.ppu_address &= ~0x1f;
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ppu_state.ppu_address ^= 0x0400;
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} else {
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ppu_state.ppu_address++;
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}
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}
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// address read_addr;
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// switch (fetch_cycle) {
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// case 1:
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// read_addr = 0x2000 + ((ppu_state.scanline / 8) * 0x20) + (ppu_state.cycle / 8);
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// ppu_state.fetch.nametable = ppu_read(read_addr);
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// break;
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// case 3:
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// read_addr = 0x23c0 + (ppu_state.cycle % 8);
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// ppu_state.fetch.attribute_table = ppu_read(read_addr);
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// break;
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// case 5:
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// read_addr = 0x1000 * ppu_read_flag(PPU_REGISTER_CTRL, PPU_CTRL_BG_PATTERN_TABLE_ADDR);
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// read_addr += ppu_state.fetch.nametable * 16 + ppu_state.scanline % 8;
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// ppu_state.fetch.pattern_table_tile_low = ppu_read(read_addr);
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// break;
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// case 7:
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// read_addr = 0x1000 * ppu_read_flag(PPU_REGISTER_CTRL, PPU_CTRL_BG_PATTERN_TABLE_ADDR);
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// read_addr += ppu_state.fetch.nametable * 16 + ppu_state.scanline % 8 + 8;
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// ppu_state.fetch.pattern_table_tile_high = ppu_read(read_addr);
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// ppu_tile_push();
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// break;
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// default:
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// break;
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// }
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}
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void ppu_visible_frame(unsigned int cycle) {
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if (!ppu_read_flag(PPU_REGISTER_MASK, PPU_MASK_SHOW_BG)) {
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// Background rendering is off
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return;
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}
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if (cycle == 0) {
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// Idle...
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} else if (cycle < 256) {
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if (ppu_read_flag(PPU_REGISTER_MASK, PPU_MASK_SHOW_BG)) {
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ppu_draw_tile();
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} else if (cycle <= 256) {
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ppu_fetch_tile();
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if (cycle <= 248) {
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address read_addr;
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byte tile_fetch_cycle = (cycle - 1) % 8;
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switch (tile_fetch_cycle) {
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case 1:
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read_addr = 0x2000 + ((ppu_state.scanline / 8) * 0x20) + (ppu_state.cycle / 8);
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ppu_state.next_tile_fetch.nametable = ppu_read(read_addr);
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break;
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case 3:
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read_addr = 0x23c0 + (ppu_state.cycle % 8);
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ppu_state.next_tile_fetch.attribute_table = ppu_read(read_addr);
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break;
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case 5:
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read_addr = 0x1000 * ppu_read_flag(PPU_REGISTER_CTRL, PPU_CTRL_BG_PATTERN_TABLE_ADDR);
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read_addr += ppu_state.next_tile_fetch.nametable * 16 + ppu_state.scanline % 8;
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ppu_state.next_tile_fetch.pattern_table_tile_low = ppu_read(read_addr);
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break;
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case 7:
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read_addr = 0x1000 * ppu_read_flag(PPU_REGISTER_CTRL, PPU_CTRL_BG_PATTERN_TABLE_ADDR);
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read_addr += ppu_state.next_tile_fetch.nametable * 16 + ppu_state.scanline % 8 + 8;
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ppu_state.next_tile_fetch.pattern_table_tile_high = ppu_read(read_addr);
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ppu_state.tile_fetch = ppu_state.next_tile_fetch;
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break;
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default:
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break;
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if (cycle == 256) {
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if ((ppu_state.ppu_address & 0x7000) != 0x7000) {
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ppu_state.ppu_address += 0x1000;
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} else {
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ppu_state.ppu_address &= ~0x7000;
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if ((ppu_state.ppu_address & 0x3e0) != 0x3a0) {
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ppu_state.ppu_address += 0x20;
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} else {
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ppu_state.ppu_address &= ~0x3e0;
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// ppu_state.ppu_address ^= 0x0800;
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}
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}
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}
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} else if (cycle <= 320) {
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// OAMADDR is cleared on sprite loading for pre-render and visible lines
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ppu_write_reg(PPU_REGISTER_OAM_ADDR, 0);
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if (cycle == 257) {
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ppu_state.ppu_address = (ppu_state.ppu_address & 0xfbe0) | (ppu_state.temp_ppu_addr & ~0xfbe0);
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ppu_state.x_scroll = 0;
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}
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} else if (cycle <= 336) {
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ppu_fetch_tile();
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}
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}
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@ -182,6 +252,8 @@ void ppu_cycle() {
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ppu_post_render(ppu_state.cycle, ppu_state.scanline);
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} else if (ppu_state.scanline == PPU_PRE_RENDER_LINE) {
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ppu_pre_render(ppu_state.cycle);
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ppu_visible_frame(ppu_state.cycle);
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ppu_state.ppu_address = ppu_state.temp_ppu_addr;
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}
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int frame_width = PPU_LINE_WIDTH;
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@ -200,101 +272,13 @@ void ppu_cycle() {
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ppu_state.scanline++;
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}
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if (ppu_state.scanline >= frame_height) {
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if (ppu_state.scanline > frame_height) {
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ppu_state.scanline = 0;
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ppu_state.frame++;
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ppu_state.odd_frame = !ppu_state.odd_frame;
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}
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}
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bool ppu_read_flag(size_t reg, byte mask) {
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return ppu_state.registers[reg] & mask;
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}
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byte ppu_read_reg(byte reg) {
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assert(reg >= 0);
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assert(reg <= PPU_REGISTER_SIZE);
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if (reg == PPU_REGISTER_STATUS) {
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ppu_state.w = false;
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byte status = ppu_state.registers[PPU_REGISTER_STATUS];
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ppu_state.registers[PPU_REGISTER_STATUS] &= ~PPU_STATUS_VBLANK;
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return status;
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}
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if (reg == PPU_REGISTER_DATA) {
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// Access to VRAM memory is slow, so reading it a first time generally return the memory at the previous address.
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// So we get the data first, then update the register.
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byte data = ppu_state.registers[reg];
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ppu_state.registers[reg] = ppu_read(ppu_state.ppu_address);
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if (ppu_state.ppu_address > 0x3eff) {
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// But the palette data is returned immediately
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data = ppu_state.registers[reg];
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}
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// We then need to increment the VRAM address
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byte increment = 1;
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if (ppu_read_flag(PPU_REGISTER_CTRL, PPU_CTRL_VRAM_ADDR_INCREMENT)) {
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increment = 32;
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}
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ppu_state.ppu_address += increment;
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ppu_state.ppu_address %= PPU_VRAM_SIZE;
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return data;
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}
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return ppu_state.registers[reg];
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}
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void ppu_write_reg(byte reg, byte data) {
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ppu_state.registers[reg] = data;
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if (reg == PPU_REGISTER_CTRL && ppu_read_flag(PPU_REGISTER_STATUS, PPU_STATUS_VBLANK) &&
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!ppu_read_flag(PPU_REGISTER_CTRL, PPU_CTRL_GEN_VBLANK_NMI) &&
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data & PPU_CTRL_GEN_VBLANK_NMI) {
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// The VBlank flag is still set, and the GEN_VBLANK_NMI was set from 0 to 1
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cpu_trigger_nmi();
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} else if (reg == PPU_REGISTER_SCROLL) {
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if (!ppu_state.w) {
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ppu_state.x = data;
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} else {
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ppu_state.t = data;
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}
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ppu_state.w = !ppu_state.w;
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} else if (reg == PPU_REGISTER_ADDR) {
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address addr = ppu_state.ppu_address;
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if (!ppu_state.w) {
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addr = data;
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} else {
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addr = data | (addr << 8);
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}
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ppu_state.ppu_address = addr % PPU_VRAM_SIZE;
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ppu_state.w = !ppu_state.w;
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} else if (reg == PPU_REGISTER_DATA) {
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address addr = ppu_state.ppu_address;
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||||
ppu_write(addr, data);
|
||||
|
||||
byte increment = 1;
|
||||
if (ppu_read_flag(PPU_REGISTER_CTRL, PPU_CTRL_VRAM_ADDR_INCREMENT)) {
|
||||
increment = 32;
|
||||
}
|
||||
|
||||
addr += increment;
|
||||
ppu_state.ppu_address = addr % PPU_VRAM_SIZE;
|
||||
} else if (reg == PPU_REGISTER_OAM_DATA) {
|
||||
byte oam_addr = ppu_state.registers[PPU_REGISTER_OAM_ADDR];
|
||||
ppu_write_reg(PPU_REGISTER_OAM_ADDR, oam_addr + 1);
|
||||
}
|
||||
|
||||
ppu_state.registers[reg] = data;
|
||||
}
|
||||
|
||||
void ppu_write_reg_oam_addr(byte data) {
|
||||
ppu_state.oam_dma_register = data;
|
||||
}
|
||||
|
||||
void ppu_write(address addr, byte data) {
|
||||
assert(addr < PPU_VRAM_SIZE);
|
||||
|
||||
|
|
@ -379,3 +363,134 @@ byte ppu_read(address addr) {
|
|||
// assert(false);
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool ppu_read_flag(size_t reg, byte mask) {
|
||||
return ppu_state.registers[reg] & mask;
|
||||
}
|
||||
|
||||
/*
|
||||
* d8888b. d88888b d888b d888888b .d8888. d888888b d88888b d8888b. .d8888.
|
||||
* 88 `8D 88' 88' Y8b `88' 88' YP `~~88~~' 88' 88 `8D 88' YP
|
||||
* 88oobY' 88ooooo 88 88 `8bo. 88 88ooooo 88oobY' `8bo.
|
||||
* 88`8b 88~~~~~ 88 ooo 88 `Y8b. 88 88~~~~~ 88`8b `Y8b.
|
||||
* 88 `88. 88. 88. ~8~ .88. db 8D 88 88. 88 `88. db 8D
|
||||
* 88 YD Y88888P Y888P Y888888P `8888Y' YP Y88888P 88 YD `8888Y'
|
||||
*/
|
||||
|
||||
void ppu_write_ctrl(byte data) {
|
||||
ppu_state.temp_ppu_addr = (ppu_state.temp_ppu_addr & 0xf3ff) | ((data & PPU_CTRL_BASE_NAMETABLE_ADDR) << 10);
|
||||
ppu_state.bg_pattern_table_addr = (data & PPU_CTRL_BG_PATTERN_TABLE_ADDR) << 0x8; // 0x0000 or 0x1000
|
||||
|
||||
ppu_state.ppu_addr_increment = (data & PPU_CTRL_VRAM_ADDR_INCREMENT) ? 0x20 : 1;
|
||||
|
||||
if (ppu_read_flag(PPU_REGISTER_STATUS, PPU_STATUS_VBLANK) &&
|
||||
!ppu_read_flag(PPU_REGISTER_CTRL, PPU_CTRL_GEN_VBLANK_NMI) &&
|
||||
data & PPU_CTRL_GEN_VBLANK_NMI) {
|
||||
// The VBlank flag is still set, and the GEN_VBLANK_NMI was set from 0 to 1
|
||||
cpu_trigger_nmi();
|
||||
}
|
||||
}
|
||||
|
||||
void ppu_write_scroll(byte data) {
|
||||
ppu_state.w = !ppu_state.w;
|
||||
|
||||
// TODO: Understand and fix with a game using scrolling
|
||||
if (ppu_state.w) {
|
||||
ppu_state.temp_ppu_addr = (ppu_state.temp_ppu_addr & 0xffe0) | (data >> 3);
|
||||
ppu_state.fine_x_scroll = data & 0x7;
|
||||
} else {
|
||||
ppu_state.temp_ppu_addr = ppu_state.temp_ppu_addr & 0xc1f;
|
||||
ppu_state.temp_ppu_addr |= (data & 0xf8) << 2;
|
||||
ppu_state.temp_ppu_addr |= (data & 0x7) << 12;
|
||||
ppu_state.y_scroll = data;
|
||||
}
|
||||
}
|
||||
|
||||
void ppu_write_addr(byte data) {
|
||||
ppu_state.w = !ppu_state.w;
|
||||
|
||||
if (ppu_state.w) {
|
||||
ppu_state.temp_ppu_addr = (ppu_state.temp_ppu_addr & 0x00ff) | (data & 0x3f) << 8;
|
||||
} else {
|
||||
ppu_state.temp_ppu_addr = (ppu_state.temp_ppu_addr & 0xff00) | data;
|
||||
ppu_state.ppu_address = ppu_state.temp_ppu_addr;
|
||||
}
|
||||
}
|
||||
|
||||
void ppu_write_data(byte data) {
|
||||
address addr = ppu_state.ppu_address;
|
||||
ppu_write(addr, data);
|
||||
|
||||
ppu_state.ppu_address = addr + ppu_state.ppu_addr_increment;
|
||||
}
|
||||
|
||||
void ppu_write_oamdata(byte data) {
|
||||
byte oam_addr = ppu_state.registers[PPU_REGISTER_OAM_ADDR];
|
||||
ppu_write_reg(PPU_REGISTER_OAM_ADDR, oam_addr + 1);
|
||||
}
|
||||
|
||||
void ppu_write_oamaddr(byte data) {
|
||||
ppu_state.oam_dma_register = data;
|
||||
}
|
||||
|
||||
void ppu_write_reg(byte reg, byte data) {
|
||||
assert(reg >= 0);
|
||||
assert(reg <= PPU_REGISTER_SIZE);
|
||||
|
||||
switch (reg) {
|
||||
case PPU_REGISTER_CTRL:
|
||||
ppu_write_ctrl(data);
|
||||
break;
|
||||
case PPU_REGISTER_SCROLL:
|
||||
ppu_write_scroll(data);
|
||||
break;
|
||||
case PPU_REGISTER_ADDR:
|
||||
ppu_write_addr(data);
|
||||
break;
|
||||
case PPU_REGISTER_DATA:
|
||||
ppu_write_data(data);
|
||||
break;
|
||||
case PPU_REGISTER_OAM_DATA:
|
||||
ppu_write_oamdata(data);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
ppu_state.registers[reg] = data;
|
||||
}
|
||||
|
||||
byte ppu_read_status() {
|
||||
ppu_state.w = false;
|
||||
byte status = ppu_state.registers[PPU_REGISTER_STATUS];
|
||||
ppu_state.registers[PPU_REGISTER_STATUS] &= ~PPU_STATUS_VBLANK;
|
||||
return status;
|
||||
}
|
||||
|
||||
byte ppu_read_data() {
|
||||
// Access to VRAM memory is slow, so reading it a first time generally return the memory at the previous address.
|
||||
// So we get the data first, then update the register.
|
||||
byte data = ppu_state.registers[PPU_REGISTER_DATA];
|
||||
ppu_state.registers[PPU_REGISTER_DATA] = ppu_read(ppu_state.ppu_address);
|
||||
if (ppu_state.ppu_address > 0x3eff) {
|
||||
// But the palette data is returned immediately
|
||||
data = ppu_state.registers[PPU_REGISTER_DATA];
|
||||
}
|
||||
|
||||
ppu_state.ppu_address = ppu_state.ppu_address + ppu_state.ppu_addr_increment;
|
||||
return data;
|
||||
}
|
||||
|
||||
byte ppu_read_reg(byte reg) {
|
||||
assert(reg >= 0);
|
||||
assert(reg <= PPU_REGISTER_SIZE);
|
||||
|
||||
switch (reg) {
|
||||
case PPU_REGISTER_STATUS:
|
||||
return ppu_read_status();
|
||||
case PPU_REGISTER_DATA:
|
||||
return ppu_read_data();
|
||||
default:
|
||||
return ppu_state.registers[reg];
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue