INes 2.0 ROM structure

core/src/cpu/mod.rs

@@ -256,5 +256,7 @@ impl Clock for Cpu {
 
         self.busy_cycle_count = instr.cycles();
         self.exec_instruction(instr);
+
+        // TODO: NMI, OAM DMA
     }
 }

core/src/cpu/operations.rs

@@ -474,12 +474,6 @@ impl Cpu {
         };
 
         self.registers.pc = target_addr;
-
-        // TODO
-        // int cycle_count = 3;
-        // if (addr_mode == ADDR_MODE_INDIRECT_JUMP) {
-        //     cycle_count = 5;
-        // }
     }
 
     /// Jump to subroutine
@@ -489,8 +483,6 @@ impl Cpu {
 
         self.stack_push_word(pc);
         self.registers.pc = target_addr;
-
-        // TODO: Cycle count
     }
 
     /// Unofficial, LDA and TSX
@@ -561,7 +553,6 @@ impl Cpu {
 
     /// No operation
     fn op_nop(&mut self, operand: Operand) {
-        // TODO: Cycle count (2)
     }
 
     /// Bitwise OR with accumulator
@@ -578,8 +569,6 @@ impl Cpu {
         let a = self.registers.a;
 
         self.stack_push(a);
-
-        // TODO: Cycle count (3)
     }
 
     /// Push status to stack
@@ -588,8 +577,6 @@ impl Cpu {
         status |= 0b00110000;
 
         self.stack_push(status);
-
-        // TODO: Cycle count (3)
     }
 
     /// Pull A from stack
@@ -599,7 +586,6 @@ impl Cpu {
         self.registers.a = a;
 
         self.set_common_flags(a);
-        // TODO: Cycle count (4)
     }
 
     /// Pull status from stack
@@ -610,7 +596,6 @@ impl Cpu {
         let result = status | current_status;
 
         self.registers.status = result;
-        // TODO: Cycle count (4)
     }
 
     /// Unofficial, ROL + AND
@@ -675,8 +660,6 @@ impl Cpu {
 
         self.registers.status = result_status;
         self.registers.pc = pc;
-
-        // TODO: Cycle count (6)
     }
 
     /// Return from subroutine
@@ -685,8 +668,6 @@ impl Cpu {
 
         let target_pc = pc.wrapping_add(1);
         self.registers.pc = target_pc;
-
-        // TODO: Cycle count (6)
     }
 
     /// Unofficial, M = A & X
@@ -720,22 +701,16 @@ impl Cpu {
     /// Set carry flag
     fn op_sec(&mut self, operand: Operand) {
         self.set_status_flag(CpuStatus::Carry, true);
-
-        // TODO: Cycle count (2)
     }
 
     /// Set decimal
     fn op_sed(&mut self, operand: Operand) {
         self.set_status_flag(CpuStatus::Decimal, true);
-
-        // TODO: Cycle count (2)
     }
 
     /// Set interrupt disable
     fn op_sei(&mut self, operand: Operand) {
         self.set_status_flag(CpuStatus::InterruptDisable, true);
-
-        // TODO: Cycle count (2)
     }
 
     /// Unofficial and unstable, M = X & (high byte + 1)

core/src/lib.rs

@@ -1,5 +1,6 @@
 mod cpu;
 mod memory;
+mod rom;
 
 pub trait Clock {
     /// Run a clock cycle

core/src/rom/ines.rs

@@ -0,0 +1,37 @@
+//! INes 2.0 Format implementation
+
+pub struct INesRom {}
+
+struct INesHeader {
+    prg_rom_size: u16,
+    chr_rom_size: u16,
+    flag_6: u8,
+    flag_7: u8,
+    mapper: u8,
+    sub_mapper: u8,
+    prg_ram_size: u8,
+    prg_nvram_size: u8,
+    chr_ram_size: u8,
+    cpu_trainer: CpuTimingMode,
+    misc_rom_count: u8,
+    default_expansion_device: u8, // vs_ppu_type: u8,
+                                  // vs_hardware_type: u8,
+}
+
+#[repr(u8)]
+enum CpuTimingMode {
+    NTSC = 0,
+    PAL = 1,
+    Multiple = 2,
+    Dendy = 3,
+}
+
+union CpuSystemType {
+    vs_system_type: VsSystemType,
+    extended_console_type: u8,
+}
+
+struct VsSystemType {
+    ppu_type: u8,
+    hardware_type: u8,
+}

core/src/rom/mod.rs

@@ -0,0 +1 @@
+mod ines;