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No commits in common. "8cfedc63d4521ec5cd260940e67958241462b7ce" and "223fb6f55d2d03e2f5c8bc17afffc8d14c51adb5" have entirely different histories.
8cfedc63d4 ... 223fb6f55d

12 changed files with 51 additions and 87 deletions
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1
.gitignore vendored
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@ -1,2 +1 @@
/target
/roms

1
.idea/nesrust.iml generated
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@ -5,7 +5,6 @@
<sourceFolder url="file://$MODULE_DIR$/core/core/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/core/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/ui/src" isTestSource="false" />
<excludeFolder url="file://$MODULE_DIR$/core/core/target" />
<excludeFolder url="file://$MODULE_DIR$/core/target" />
<excludeFolder url="file://$MODULE_DIR$/target" />

8
Cargo.lock generated
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@ -208,14 +208,6 @@ dependencies = [
"time-core",
]
[[package]]
name = "ui"
version = "0.1.0"
dependencies = [
"core",
"simplelog",
]
[[package]]
name = "unicode-ident"
version = "1.0.14"

2
Cargo.toml
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@ -6,4 +6,4 @@
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[workspace]
members = ["core", "ui"]
members = ["core"]

8
core/src/cpu/disassembler.rs
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@ -2,14 +2,14 @@ use crate::cpu::op::AddressingMode::*;
use crate::cpu::op::{AddressingMode, Instruction};
use crate::cpu::Cpu;
impl Cpu {
impl Cpu<'_> {
pub fn disassemble_next_instr(&self) {
let registers = self.registers;
let op_code = self.memory_bus.borrow().get_byte(registers.pc) as usize;
let op_code = self.memory_bus.get_byte(registers.pc);
let instr: Instruction = Self::INSTRUCTIONS[op_code];
let operation = instr.op().to_string();
let addr_mode = self.disassemble_addr_mode(instr.addr_mode(), registers.pc);
let addr_mode = self.disassemble_addr_mode(instr.addr_mode());
dbg!(
"DIS {:#04x} - {:#02x} {:?} {:?} - A {:#02x}, X {:#02x}, Y {:#02x}, SP: {:#02x}, F: {:#02x}",
@ -26,7 +26,7 @@ impl Cpu {
}
fn disassemble_addr_mode(&self, addr_mode: AddressingMode, pc: u16) -> String {
let word_peek = self.memory_bus.borrow().get_word(pc);
let word_peek = self.memory_bus.get_word(pc);
let byte_peek = (word_peek & 0xFF) as u8;
match addr_mode {

33
core/src/cpu/mod.rs
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@ -2,7 +2,6 @@ mod disassembler;
mod op;
mod operations;
use std::cell::RefCell;
use crate::memory::MemoryBus;
use crate::Clock;
use bitflags::bitflags;
@ -10,18 +9,18 @@ use bitflags::bitflags;
const STACK_ADDR: u16 = 0x0100;
/// Represents a 6502 CPU
pub struct Cpu {
struct Cpu<'a> {
/// The registers of the CPU
registers: CpuRegisters,
/// The memory bus accessible by the CPU
memory_bus: RefCell<MemoryBus>,
memory_bus: &'a MemoryBus,
/// The number of cycles ran on the CPU
cycle: usize,
cycle: u32,
/// The amount of cycles the CPU will be busy for (won't execute any instruction)
busy_cycle_count: usize,
busy_cycle_count: u16,
/// Whether an OAM DMA was triggered (data transfer to the PPU OAM memory)
oam_dma_triggered: bool,
@ -132,8 +131,8 @@ pub trait CpuInternals {
fn stack_pop_context(&mut self);
}
impl Cpu {
pub fn new(memory_bus: RefCell<MemoryBus>) -> Self {
impl<'a> Cpu<'a> {
pub fn new(memory_bus: &mut MemoryBus) -> Self {
Cpu {
registers: CpuRegisters {
pc: 0x8000,
@ -152,9 +151,9 @@ impl Cpu {
}
}
impl CpuInternals for Cpu {
impl CpuInternals for Cpu<'_> {
fn get_status_flag(&self, flag: CpuStatus) -> bool {
self.registers.status & flag.bits() > 0
*self.registers.status & flag
}
fn get_status_flag_u8(&self, flag: CpuStatus) -> u8 {
@ -167,14 +166,14 @@ impl CpuInternals for Cpu {
}
fn program_get_next_byte(&mut self) -> u8 {
let byte = self.memory_bus.borrow().get_byte(self.registers.pc);
let byte = self.memory_bus.get_byte(self.registers.pc);
self.registers.pc += 1;
byte
}
fn program_get_next_word(&mut self) -> u16 {
let word = self.memory_bus.borrow().get_word(self.registers.pc);
let word = self.memory_bus.get_word(self.registers.pc);
self.registers.pc += 2;
word
@ -182,9 +181,9 @@ impl CpuInternals for Cpu {
fn set_status_flag(&mut self, flag: CpuStatus, set: bool) {
if set {
self.registers.status |= flag.bits();
*self.registers.status |= flag;
} else {
self.registers.status &= !flag.bits();
*self.registers.status &= !flag;
}
}
@ -197,7 +196,7 @@ impl CpuInternals for Cpu {
assert!(self.registers.sp > 0);
let addr = STACK_ADDR | self.registers.sp as u16;
self.memory_bus.borrow_mut().set_byte(addr, value);
self.memory_bus.set_byte(addr, value);
self.registers.sp -= 1;
}
@ -212,7 +211,7 @@ impl CpuInternals for Cpu {
self.registers.sp += 1;
let addr = STACK_ADDR | self.registers.sp as u16;
self.memory_bus.borrow().get_byte(addr)
self.memory_bus.get_byte(addr)
}
fn stack_pop_word(&mut self) -> u16 {
@ -241,7 +240,7 @@ impl CpuInternals for Cpu {
}
}
impl Clock for Cpu {
impl Clock for Cpu<'_> {
fn cycle(&mut self) {
self.cycle += 1;
@ -253,7 +252,7 @@ impl Clock for Cpu {
self.disassemble_next_instr();
let op_code = self.program_get_next_byte();
let instr = Self::INSTRUCTIONS[op_code as usize];
let instr = Self::INSTRUCTIONS[op_code];
self.busy_cycle_count = instr.cycles();
self.exec_instruction(instr);

38
core/src/cpu/op.rs
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@ -31,10 +31,13 @@ use OperationType::{
};
/// CPU Instruction.
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
pub struct Instruction(u8, AddressingMode, OperationType, usize);
impl Instruction {
pub const fn opcode(&self) -> u8 {
self.0
}
pub const fn addr_mode(&self) -> AddressingMode {
self.1
}
@ -66,7 +69,7 @@ impl Operand {
self.value as u8
}
pub fn is_address(&self) -> bool {
pub const fn is_address(&self) -> bool {
self.operand_type == OperandType::Address
}
@ -76,7 +79,7 @@ impl Operand {
OperandType::Immediate => self.value_u8(),
OperandType::Address => {
let addr = self.value;
cpu.memory_bus.borrow().get_byte(addr)
cpu.memory_bus.get_byte(addr)
}
}
}
@ -86,7 +89,7 @@ impl Operand {
OperandType::Accumulator => cpu.registers.a = value,
OperandType::Address => {
let addr = self.value;
cpu.memory_bus.borrow_mut().set_byte(addr, value);
cpu.memory_bus.set_byte(addr, value);
}
OperandType::Immediate => unreachable!("Cannot write to immediate operand"),
}
@ -94,7 +97,7 @@ impl Operand {
}
// Operands
impl Cpu {
impl Cpu<'_> {
/// 16x16 grid of 6502 opcodes. Matches datasheet matrix for easy lookup
#[rustfmt::skip]
pub const INSTRUCTIONS: [Instruction; 256] = [
@ -116,6 +119,13 @@ impl Cpu {
Instruction(0xF0, REL, BEQ, 2), Instruction(0xF1, IDY, SBC, 5), Instruction(0xF2, IMP, STP, 2), Instruction(0xF3, IDY, ISB, 8), Instruction(0xF4, ZPX, NOP, 4), Instruction(0xF5, ZPX, SBC, 4), Instruction(0xF6, ZPX, INC, 6), Instruction(0xF7, ZPX, ISB, 6), Instruction(0xF8, IMP, SED, 2), Instruction(0xF9, ABY, SBC, 4), Instruction(0xFA, IMP, NOP, 2), Instruction(0xFB, ABY, ISB, 7), Instruction(0xFC, ABX, NOP, 4), Instruction(0xFD, ABX, SBC, 4), Instruction(0xFE, ABX, INC, 7), Instruction(0xFF, ABX, ISB, 7),
];
pub fn read_next_instruction(&mut self) -> Instruction {
let op_code = self.program_get_next_byte();
let instruction = Instruction[op_code];
instruction
}
/// Decodes the next operand in memory
///
/// # Arguments
@ -216,11 +226,11 @@ impl Cpu {
if ref_addr & 0xFF == 0xFF {
// Error in NES CPU for JMP op
let low = self.memory_bus.borrow().get_byte(ref_addr) as u16;
let high = self.memory_bus.borrow().get_byte(ref_addr & 0xFF00) as u16;
let low = self.memory_bus.get_byte(ref_addr) as u16;
let high = self.memory_bus.get_byte(ref_addr & 0xFF00) as u16;
low + (high << 8)
} else {
self.memory_bus.borrow().get_word(ref_addr)
self.memory_bus.get_word(ref_addr)
}
}
@ -229,17 +239,17 @@ impl Cpu {
let mut ref_addr = self.program_get_next_byte() as u16;
ref_addr += self.registers.x as u16;
let low = self.memory_bus.borrow().get_byte(ref_addr & 0xFF) as u16;
let high = self.memory_bus.borrow().get_byte((ref_addr + 1) & 0xFF) as u16;
let low = self.memory_bus.get_byte(ref_addr & 0xFF) as u16;
let high = self.memory_bus.get_byte((ref_addr + 1) & 0xFF) as u16;
low + (high << 8)
}
/// (d),y - PEEK(byte) + Y
fn operand_addr_indy(&mut self, page_crossed: &mut bool) -> u16 {
let ref_addr = self.program_get_next_byte() as u16;
let mut ref_addr = self.program_get_next_byte() as u16;
let low = self.memory_bus.borrow().get_byte(ref_addr) as u16;
let high = self.memory_bus.borrow().get_byte((ref_addr + 1) & 0xFF) as u16;
let low = self.memory_bus.get_byte(ref_addr) as u16;
let high = self.memory_bus.get_byte((ref_addr + 1) & 0xFF) as u16;
let addr = low + (high << 8);
let incr_addr = addr + self.registers.y as u16;
@ -255,7 +265,7 @@ impl Cpu {
// The offset is signed
let positive_offset = offset & 0x7F;
if offset & 0x80 > 0 {
if offset & 0x80 {
base_addr.wrapping_sub(positive_offset)
} else {
base_addr.wrapping_add(positive_offset)

16
core/src/cpu/operations.rs
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@ -7,7 +7,7 @@ fn is_sign_overflow(val1: u8, val2: u8, result: u8) -> bool {
(val1 & 0x80 == val2 & 0x80) && (val1 & 0x80 != result & 0x80)
}
impl Cpu {
impl Cpu<'_> {
pub fn exec_instruction(&mut self, instr: Instruction) {
let operand = self.operand_decode(instr.addr_mode());
if operand.is_page_crossing {
@ -322,11 +322,6 @@ impl Cpu {
self.set_status_flag(CpuStatus::Carry, false);
}
/// Clear decimal flag
fn op_cld(&mut self, operand: Operand) {
self.set_status_flag(CpuStatus::Decimal, false);
}
/// Clear interrupt disable flag
fn op_cli(&mut self, operand: Operand) {
self.set_status_flag(CpuStatus::InterruptDisable, false);
@ -475,7 +470,7 @@ impl Cpu {
value
} else {
assert_eq!(addr_mode, AddressingMode::IND);
self.memory_bus.borrow().get_word(value)
self.memory_bus.get_word(value)
};
self.registers.pc = target_addr;
@ -845,13 +840,6 @@ impl Cpu {
self.set_common_flags(x);
}
/// Transfer X to stack pointer
fn op_txs(&mut self, operand: Operand) {
let x = self.registers.x;
self.registers.sp = x;
}
/// Transfer Y to A
fn op_tya(&mut self, operand: Operand) {
let y = self.registers.y;

2
core/src/lib.rs
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@ -1,6 +1,6 @@
mod cpu;
mod memory;
pub mod rom;
mod rom;
pub trait Clock {
/// Run a clock cycle

7
core/src/rom/mod.rs
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@ -71,7 +71,7 @@ pub trait RomLoader {
}
impl Rom {
pub fn read(path: &str) -> Result<Rom, RomReadError> {
fn read(path: &str) -> Result<(), RomReadError> {
info!("ROM - Reading file from {}", path);
let content = match fs::read(path) {
@ -95,12 +95,11 @@ impl Rom {
debug!("ROM - PRG ROM: {} bytes, CHR ROM: {} bytes", rom.prg_rom_size, rom.chr_rom_size);
info!("ROM - Loading successful");
Ok(rom)
Ok(())
}
}
#[derive(Debug)]
pub enum RomReadError {
enum RomReadError {
FormatNotSupported,
Io(std::io::Error),
InvalidHeader(String),

10
ui/Cargo.toml
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@ -1,10 +0,0 @@
[package]
name = "ui"
version = "0.1.0"
edition = "2021"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[dependencies]
core = { path = "../core" }
simplelog = { version = "^0.12.0", features = ["paris"] }

12
ui/src/main.rs
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@ -1,12 +0,0 @@
use core::rom::Rom;
use simplelog::*;
fn main() {
CombinedLogger::init(vec![
TermLogger::new(LevelFilter::Debug, Config::default(), TerminalMode::Mixed, ColorChoice::Auto),
]).unwrap();
let path = "./roms/dk.nes";
let rom = Rom::read(path).expect("Failed to read ROM file");
print!("Do stuff");
}